1. Field of the Invention
The present invention relates to a non-volatile semiconductor storage device and a shipment test therefor, and more specifically, to a test circuit and method used for a characteristic test of a non-volatile storage element in a non-volatile semiconductor storage device having an ECC circuit mounted thereon.
2. Description of the Related Art
A related art non-volatile semiconductor storage device having an ECC circuit mounted thereon is described. FIG. 8 is a circuit diagram illustrating the related art non-volatile semiconductor storage device having the ECC circuit mounted thereon.
The related art non-volatile semiconductor storage device having the ECC circuit mounted thereon includes an ECC encoder 81, a data cell array 82, a check bit cell array 83, a syndrome decoder 84, and an error correcting section 85.
At the time of data writing, the related art non-volatile semiconductor storage device operates as follows. The data cell array 82 receives and stores write data WD. The ECC encoder 81 receives the write data WD to generate an error correcting code (ECC) corresponding to the write data WD, and outputs the error correcting code to the check bit cell array 83. The check bit cell array 83 receives and stores the error correcting code.
At the time of data read-out, the related art non-volatile semiconductor storage device operates as follows. The syndrome decoder 84 performs error detection with use of the write data WD of the data cell array 82 and the error correcting code of the check bit cell array 83 to generate syndrome data, and outputs the syndrome data to the error correcting section 85. The error correcting section 85 corrects the error with use of the write data WD, the error correcting code, and the syndrome data, and outputs read data RD (for example, see Japanese Patent Application Laid-open No. 2001-23394).
However, the related art semiconductor storage device having the ECC circuit mounted thereon includes a circuit for performing error detection and error correction of the write data WD and the error correcting code in the error correcting section 85, and hence has a problem in that the circuit scale is large.
In normal data read-out, only error correction of the write data WD is required, and error detection and error correction of the error correcting code are unnecessary. However, in shipment inspection, error detection of the error correcting code is required, that is, initial failure of the check bit cell array is required to be detected.